Tegra: common: drivers: fix MISRA defects

Main fixes:

Add suffix U for constant [Rule 10.1]

Match the operands type [Rule 10.4]

Use UL replace U for that constant define that need do "~"
operation [Rule 12.4]

Voided non c-library functions whose return types are not used
 [Rule 17.7]

Change-Id: Ia1e814ca3890eab7904be9c79030502408f30936
Signed-off-by: Anthony Zhou <[email protected]>

diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
index de431b75b66aa9bb1c972fe7b63128e358a9381e..ba6d283eeb959c6ebdbba41f05884a08020b78da 100644 (file)
--- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
+++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
@@ -287,7 +287,7 @@ static void tegra_memctrl_reconfig_mss_clients(void)
 
 static void tegra_memctrl_set_overrides(void)
 {
-       tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings();
+       const tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings();
        const mc_txn_override_cfg_t *mc_txn_override_cfgs;
        uint32_t num_txn_override_cfgs;
        uint32_t i, val;
@@ -347,7 +347,7 @@ void tegra_memctrl_setup(void)
        uint32_t num_streamid_override_regs;
        const mc_streamid_security_cfg_t *mc_streamid_sec_cfgs;
        uint32_t num_streamid_sec_cfgs;
-       tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings();
+       const tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings();
        uint32_t i;
 
        INFO("Tegra Memory Controller (v2)\n");
@@ -525,7 +525,7 @@ void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes)
         * at all.
         */
        val = tegra_mc_read_32(MC_TZRAM_CARVEOUT_CFG);
-       val &= ~MC_GSC_ENABLE_TZ_LOCK_BIT;
+       val &= (uint32_t)~MC_GSC_ENABLE_TZ_LOCK_BIT;
        val |= MC_GSC_LOCK_CFG_SETTINGS_BIT;
        tegra_mc_write_32(MC_TZRAM_CARVEOUT_CFG, val);
 
@@ -603,7 +603,7 @@ static void tegra_clear_videomem(uintptr_t non_overlap_area_start,
        /*
         * Map the NS memory first, clean it and then unmap it.
         */
-       mmap_add_dynamic_region(non_overlap_area_start, /* PA */
+       (void)mmap_add_dynamic_region(non_overlap_area_start, /* PA */
                                non_overlap_area_start, /* VA */
                                non_overlap_area_size, /* size */
                                MT_NS | MT_RW | MT_EXECUTE_NEVER); /* attrs */
@@ -611,7 +611,7 @@ static void tegra_clear_videomem(uintptr_t non_overlap_area_start,
        zero_normalmem((void *)non_overlap_area_start, non_overlap_area_size);
        flush_dcache_range(non_overlap_area_start, non_overlap_area_size);
 
-       mmap_remove_dynamic_region(non_overlap_area_start,
+       (void)mmap_remove_dynamic_region(non_overlap_area_start,
                non_overlap_area_size);
 }
 
@@ -658,17 +658,19 @@ void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes)
         */
        INFO("Cleaning previous Video Memory Carveout\n");
 
-       if (phys_base > vmem_end_old || video_mem_base > vmem_end_new) {
+       if ((phys_base > vmem_end_old) || (video_mem_base > vmem_end_new)) {
                tegra_clear_videomem(video_mem_base,
-                                    (uint64_t)video_mem_size_mb << 20);
+                                    (uint32_t)video_mem_size_mb << 20U);
        } else {
                if (video_mem_base < phys_base) {
                        non_overlap_area_size = phys_base - video_mem_base;
-                       tegra_clear_videomem(video_mem_base, non_overlap_area_size);
+                       tegra_clear_videomem(video_mem_base,
+                                       (uint32_t)non_overlap_area_size);
                }
                if (vmem_end_old > vmem_end_new) {
                        non_overlap_area_size = vmem_end_old - vmem_end_new;
-                       tegra_clear_videomem(vmem_end_new, non_overlap_area_size);
+                       tegra_clear_videomem(vmem_end_new,
+                                       (uint32_t)non_overlap_area_size);
                }
        }
 

diff --git a/plat/nvidia/tegra/common/drivers/smmu/smmu.c b/plat/nvidia/tegra/common/drivers/smmu/smmu.c
index 610f32f1eb56561312bec02b5b2c467ff46758f7..bff95d7ce2e7321aa6fe4b1d4111a69885c676ac 100644 (file)
--- a/plat/nvidia/tegra/common/drivers/smmu/smmu.c
+++ b/plat/nvidia/tegra/common/drivers/smmu/smmu.c
@@ -26,40 +26,48 @@ enum {
 
 static uint32_t tegra_smmu_read_32(uint32_t smmu_id, uint32_t off)
 {
+       uint32_t ret = 0U;
+
 #if defined(TEGRA_SMMU0_BASE)
-       if (smmu_id == TEGRA_SMMU0)
-               return mmio_read_32(TEGRA_SMMU0_BASE + off);
+       if (smmu_id == TEGRA_SMMU0) {
+               ret = mmio_read_32(TEGRA_SMMU0_BASE + (uint64_t)off);
+       }
 #endif
 
 #if defined(TEGRA_SMMU1_BASE)
-       if (smmu_id == TEGRA_SMMU1)
-               return mmio_read_32(TEGRA_SMMU1_BASE + off);
+       if (smmu_id == TEGRA_SMMU1) {
+               ret = mmio_read_32(TEGRA_SMMU1_BASE + (uint64_t)off);
+       }
 #endif
 
 #if defined(TEGRA_SMMU2_BASE)
-       if (smmu_id == TEGRA_SMMU2)
-               return mmio_read_32(TEGRA_SMMU2_BASE + off);
+       if (smmu_id == TEGRA_SMMU2) {
+               ret = mmio_read_32(TEGRA_SMMU2_BASE + (uint64_t)off);
+       }
 #endif
 
-       return 0;
+       return ret;
 }
 
 static void tegra_smmu_write_32(uint32_t smmu_id,
                        uint32_t off, uint32_t val)
 {
 #if defined(TEGRA_SMMU0_BASE)
-       if (smmu_id == TEGRA_SMMU0)
-               mmio_write_32(TEGRA_SMMU0_BASE + off, val);
+       if (smmu_id == TEGRA_SMMU0) {
+               mmio_write_32(TEGRA_SMMU0_BASE + (uint64_t)off, val);
+       }
 #endif
 
 #if defined(TEGRA_SMMU1_BASE)
-       if (smmu_id == TEGRA_SMMU1)
-               mmio_write_32(TEGRA_SMMU1_BASE + off, val);
+       if (smmu_id == TEGRA_SMMU1) {
+               mmio_write_32(TEGRA_SMMU1_BASE + (uint64_t)off, val);
+       }
 #endif
 
 #if defined(TEGRA_SMMU2_BASE)
-       if (smmu_id == TEGRA_SMMU2)
-               mmio_write_32(TEGRA_SMMU2_BASE + off, val);
+       if (smmu_id == TEGRA_SMMU2) {
+               mmio_write_32(TEGRA_SMMU2_BASE + (uint64_t)off, val);
+       }
 #endif
 }
 
@@ -70,16 +78,16 @@ void tegra_smmu_save_context(uint64_t smmu_ctx_addr)
 {
        uint32_t i, num_entries = 0;
        smmu_regs_t *smmu_ctx_regs;
-       plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
+       const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
        uint64_t tzdram_base = params_from_bl2->tzdram_base;
        uint64_t tzdram_end = tzdram_base + params_from_bl2->tzdram_size;
        uint32_t reg_id1, pgshift, cb_size;
 
        /* sanity check SMMU settings c*/
        reg_id1 = mmio_read_32((TEGRA_SMMU0_BASE + SMMU_GNSR0_IDR1));
-       pgshift = (reg_id1 & ID1_PAGESIZE) ? 16 : 12;
-       cb_size = (2 << pgshift) * \
-       (1 << (((reg_id1 >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1));
+       pgshift = ((reg_id1 & ID1_PAGESIZE) != 0U) ? 16U : 12U;
+       cb_size = (2UL << pgshift) * \
+       (1UL << (((reg_id1 >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1UL));
 
        assert(!((pgshift != PGSHIFT) || (cb_size != CB_SIZE)));
        assert((smmu_ctx_addr >= tzdram_base) && (smmu_ctx_addr <= tzdram_end));
@@ -98,8 +106,9 @@ void tegra_smmu_save_context(uint64_t smmu_ctx_addr)
        }
 
        /* panic if the sizes do not match */
-       if (num_entries != smmu_ctx_regs[0].val)
+       if (num_entries != smmu_ctx_regs[0].val) {
                panic();
+       }
 
        /* save SMMU register values */
        for (i = 1; i < num_entries; i++)
@@ -109,8 +118,8 @@ void tegra_smmu_save_context(uint64_t smmu_ctx_addr)
        num_entries++;
 
        /* Save SMMU config settings */
-       memcpy16((void *)(uintptr_t)smmu_ctx_addr, (void *)smmu_ctx_regs,
-                (sizeof(smmu_regs_t) * num_entries));
+       (void)memcpy16((uint8_t *)smmu_ctx_addr, (uint8_t *)smmu_ctx_regs,
+                       (sizeof(smmu_regs_t) * num_entries));
 
        /* save the SMMU table address */
        mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV11_LO,

diff --git a/plat/nvidia/tegra/include/drivers/memctrl_v2.h b/plat/nvidia/tegra/include/drivers/memctrl_v2.h
index ffe5269a8086db183ff840771a57397cb8634e66..4c21b97d4649b9f5b4e59358ba2131389b813b74 100644 (file)
--- a/plat/nvidia/tegra/include/drivers/memctrl_v2.h
+++ b/plat/nvidia/tegra/include/drivers/memctrl_v2.h
@@ -98,7 +98,7 @@
 /*******************************************************************************
  * Macro to calculate Security cfg register addr from StreamID Override register
  ******************************************************************************/
-#define MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(addr) (addr + sizeof(uint32_t))
+#define MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(addr) ((addr) + sizeof(uint32_t))
 
 #define MC_TXN_OVERRIDE_CONFIG_COH_PATH_NO_OVERRIDE_SO_DEV             (0UL << 4)
 #define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_NON_COHERENT_SO_DEV      (1UL << 4)
@@ -406,8 +406,8 @@ static inline void tegra_mc_streamid_write_32(uint32_t off, uint32_t val)
        { \
                mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \
                        (TSA_CONFIG_STATIC0_CSW_##client##_RESET & \
-                        ~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \
-                       TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \
+                        (uint32_t)~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \
+                       (uint32_t)TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \
        }
 
 #define mc_set_txn_override(client, normal_axi_id, so_dev_axi_id, normal_override, so_dev_override) \

diff --git a/plat/nvidia/tegra/include/drivers/smmu.h b/plat/nvidia/tegra/include/drivers/smmu.h
index 9582a67ed376c799723e08797c245357d85406ee..1d04ef0bf342c198d9449e9cd42bae1f35e1b060 100644 (file)
--- a/plat/nvidia/tegra/include/drivers/smmu.h
+++ b/plat/nvidia/tegra/include/drivers/smmu.h
@@ -586,7 +586,7 @@
 /*******************************************************************************
  * SMMU Global Aux. Control Register
  ******************************************************************************/
-#define SMMU_CBn_ACTLR_CPRE_BIT                        (1U << 1)
+#define SMMU_CBn_ACTLR_CPRE_BIT                        (1UL << 1UL)
 
 /*******************************************************************************
  * SMMU configuration constants

diff --git a/plat/nvidia/tegra/include/t186/tegra_def.h b/plat/nvidia/tegra/include/t186/tegra_def.h
index 9bc95c1cc34a8bcd05abe9041c92debc91970df5..4cc7802c7e10ee8aa32b1f6f33f46b1da7c0c710 100644 (file)
--- a/plat/nvidia/tegra/include/t186/tegra_def.h
+++ b/plat/nvidia/tegra/include/t186/tegra_def.h
@@ -112,8 +112,8 @@
 #define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW              U(0x15018)
 #define  TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET       U(0x1100)
 
-#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK           (U(0x3) << 11)
-#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU                (U(0) << 11)
+#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK           (ULL(0x3) << 11)
+#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU                (ULL(0) << 11)
 
 /*******************************************************************************
  * Tegra General Purpose Centralised DMA constants
@@ -129,7 +129,7 @@
 /* General Security Carveout register macros */
 #define MC_GSC_CONFIG_REGS_SIZE                U(0x40)
 #define MC_GSC_LOCK_CFG_SETTINGS_BIT   (U(1) << 1)
-#define MC_GSC_ENABLE_TZ_LOCK_BIT      (U(1) << 0)
+#define MC_GSC_ENABLE_TZ_LOCK_BIT      (ULL(1) << 0)
 #define MC_GSC_SIZE_RANGE_4KB_SHIFT    U(27)
 #define MC_GSC_BASE_LO_SHIFT           U(12)
 #define MC_GSC_BASE_LO_MASK            U(0xFFFFF)

diff --git a/plat/nvidia/tegra/include/tegra_platform.h b/plat/nvidia/tegra/include/tegra_platform.h
index 1e7ba165c619f32fe5d5d26771f3380b37ddddc8..13c92e0ebde63a1fc649470b0794a19eaf58adf6 100644 (file)
--- a/plat/nvidia/tegra/include/tegra_platform.h
+++ b/plat/nvidia/tegra/include/tegra_platform.h
@@ -46,7 +46,6 @@ bool tegra_chipid_is_t186(void);
 bool tegra_chipid_is_t210(void);
 bool tegra_chipid_is_t210_b01(void);
 
-
 /*
  * Tegra platform identifiers
  */